1. Field of the Invention
The invention relates to orthogonal frequency division multiplexing systems, particularly to a symbol timing synchronization system for orthogonal frequency division multiplexing systems.
2. Description of the Related Art
In orthogonal frequency division multiplexing (OFDM) systems, the symbol timing synchronization of the receiving end is an essential issue. Referring to U.S. Pat. No. 5,991,289 and Taiwan Patent Publication No. 400675, wherein a correlator is used to obtain the correlation between samples, the phase value of the correlation is obtained by an arithmetic device, and the transition point of phases output by the arithmetic device or the maximum of the output phase is detected through a detecting device, so as to obtain the correct symbol timing synchronization point and achieve the timing synchronization.
Nevertheless, according to Taiwan Patent Publication No.429719, the timing synchronization point is obtained by the frequency domain correlation. Taiwan Patent Publication No. 421928 utilizes that when the delay of time domain in the multi-carrier digital modulation system transformed into the frequency domain, it will be changed into another appended carrier signal, and because the carrier frequency offset is proportional to the time delay length produced by multi-path interference, the time delay length can be precisely detected by this relation, thereby achieving the symbol timing synchronization.
With reference to FIG. 1, a schematic view of a conventional OFDM system 10 is shown. The conventional OFDM system 10 comprises a transmitting end serial-to-parallel circuit 11, an inverse fast Fourier transformer 12, a transmitting end parallel-to-serial circuit 13, a Cyclic Prefix (CP) inserter 14, a channel 15, a CP remover 16, a receiving end serial-to-parallel circuit 17, a fast Fourier transformer 18 and a receiving end parallel-to-serial circuit 19. Wherein the transmitting end serial-to-parallel circuit 11, the inverse fast Fourier transformer 12, the transmitting end parallel-to-serial circuit 13, the CP inserter 14 and the channel 15 are disposed on the transmitting end of the OFDM system 10. The CP remover 16, the receiving end serial-to-parallel circuit 17, the fast Fourier transformer 18 and the receiving end parallel-to-serial circuit 19 are disposed on the receiving end of the OFDM system 10.
On the receiving end of a conventional OFDM system, the timing of each symbol must be synchronized. However, the environment of wireless communication is complex and changes rapidly so that an ideal timing synchronization can't be achieved. When the timing synchronization can't reach an ideal timing point, a timing error tends to occur. If the timing error is within the acceptable range of the OFDM system, the performance of the system will not be seriously affected. However, once the timing error is beyond the acceptable range, the performance of the system will be affected seriously, thereby producing a series of reductions in the system performance.
Furthermore, a timing error occurs when the timing synchronization can't be achieved. If the timing error is beyond the acceptable range, the received symbol through the fast Fourier Transformer 18 has not only a phase error but also the Inter-Symbol Interference (ISI), and the ISI effect serially and seriously affects the performance of the system. The disadvantage in the conventional technique is that when Fourier transform demodulation are performed on the receiving end, if it is found that a symbol has an ISI, the OFDM system does not eliminate the ISI effect, and therefore the performance of the whole system is affected.
Therefore, there is a need to provide a creative and progressive symbol timing synchronization system to solve the problems mentioned above.